/* 
 * --------------------
 * Company					: LUOYANG GINGKO TECHNOLOGY CO.,LTD.
 * BBS						: http://www.eeschool.org
 * --------------------
 * Project Name			: single_port_ram
 * Module Name				: single_port_ram
 * Description				: The codes of "single_port_ram"
 * --------------------
 * Tool Versions			: Quartus II 13.1
 * Target Device			: Cyclone IV E  EP4CE10F17C8
 * --------------------
 * Engineer					: xiaorenwu
 * Revision					: V0.0
 * Created Date			: 2014-04-26
 * --------------------
 * Engineer					:
 * Revision					:
 * Modified Date			:
 * --------------------
 * Additional Comments	: SDRAM_Model	W9812G2IH
 * 
 * --------------------
 */
 //--------------------------Module_single_port_ram---------------------------//
	module single_port_ram(
							input CLK_25M,
							input WR,
							input RD,
							input CS0,
							inout [15:0]DB,
							input [24:16]A
							);
//--------------------------pll---------------------------//	
	/*例化MY_PLL模块,输出100M时钟*/
	my_pll  		u1(
						.inclk0(CLK_25M),
						.c0(PLL_100M)
						);
						
//--------------------------ram---------------------------//	
	/*例化ram块*/
	my_ram      u2(											
						.address(A),
						.clock(clk),
						.data(DB),
						.wren(!wr),
						.rden(!rd),
						.q(DB_OUT),
						);
	wire [15:0]DB_OUT;
	
//--------------------------RST_n---------------------------//  
	/*复位信号,10个周期后rst_n置1*/
	reg [3:0] cnt_rst = 4'd0;
	reg rst_n;
	always @(posedge CLK_25M)
		if(cnt_rst == 4'd10)
			begin
				rst_n <= 1'd1;
				cnt_rst <= 4'd10;
			end
		else
			cnt_rst <= cnt_rst + 1'd1;
			
//--------------------------fsmc---------------------------//
	wire rd = (CS0 | RD);		 //提取读信号
	wire wr = (CS0 | WR);       //提取写信号
	
	reg wr_clk1,wr_clk2;
	always @(posedge PLL_100M or negedge rst_n)
		begin
			if(!rst_n)
				begin
					wr_clk1 <= 1'd1;
					wr_clk2 <= 1'd1;
				end
			else
				{wr_clk2,wr_clk1} <= {wr_clk1,wr};	//提取写时钟
		end

	wire clk = (!wr_clk2 | !rd);
	assign DB = !rd ? DB_OUT : 16'hzzzz;	
	
	
//-----------------------endmodule-----------------------//
endmodule
